EunSeong Lee Portfolio

Project
Study
- AI Algorithm Structure
  - LAB
- ASIC FrontEnd
  - post-01
  - post-02
- Arm Architecture
  - post-01
- CMOS VLSI Design
  - LAB
  - THEORY
- CPU Design
  - CODE
  - LAB
  - THEORY
- FPGA
  - LAB
  - THEORY
comment system
Home
markdown
portfolio

Contact

Copyright © 2024 | Yankos

Home > Study > CPU Design > CODE

Please wait ...

CODE

DedicatedProcessor ALUOP
DedicatedProcessor ALUOP ✅ DedicatedProcessor_ALUOP.sv `timescale 1ns / 1ps module DedicatedProcessor_ALUOP( input logic clk, input logic reset, output logic [7:0] OutPort ); logic RFSrcMuxSel; logic [2:0] RAddr1; logic [2:0] RAddr2; logic [2:0] WAddr; logic [1:0] AluOpMuxSel; logic we; logic Lt; logic OutPortEn; DataPath U_DataPath ( .clk (clk), .reset (reset), .RFSrcMuxSel(RFSrcMuxSel), .RAddr1 (RAddr1), .RAddr2 (RAddr2), .WAddr (WAddr), .AluOpMuxSel(AluOpMuxSel), .we (we), .Lt (Lt), .OutPortEn (OutPortEn), .OutPort (OutPort) ); ControlUnit U_ControlUnit ( .clk (clk), .reset (reset), .RFSrcMuxSel(RFSrcMuxSel), .RAddr1 (RAddr1), .RAddr2 (RAddr2), .WAddr (WAddr), .AluOpMuxSel(AluOpMuxSel), .we (we), .Lt (Lt), .OutPortEn (OutPortEn) ); endmodule ✅ DataPath.sv `timescale 1ns / 1ps module DataPath ( input logic clk, input logic reset, input logic RFSrcMuxSel, input logic [2:0] RAddr1, input logic [2:0] RAddr2, input logic [2:0] WAddr, input logic [1:0] AluOpMuxSel, input logic we, output logic Lt, input logic OutPortEn, output logic [7:0] OutPort ); logic [7:0] AdderResult, RFSrcMuxOut; logic [7:0] RData1, RData2; mux_2x1 U_RFSrcMux ( .sel(RFSrcMuxSel), .x0 (AdderResult), .x1 (1), .y (RFSrcMuxOut) ); RegFile U_RegFile ( .clk (clk), .RAddr1(RAddr1), .RAddr2(RAddr2), .WAddr (WAddr), .we (we), .WData (RFSrcMuxOut), .RData1(RData1), .RData2(RData2) ); comparator U_comparator ( .a (RData1), .b (RData2), .lt (Lt) ); alu_op U_ALU_OP ( .x0 (RData1), .x1 (RData2), .AluOpMuxSel(AluOpMuxSel), .y (AdderResult) ); register U_OutPort ( .clk (clk), .reset(reset), .en (OutPortEn), .d (RData1), .q (OutPort) ); endmodule ✅ alu_op 추가 module alu_op ( input logic [7:0] x0, input logic [7:0] x1, input logic [1:0] AluOpMuxSel, output logic [7:0] y ); always_comb begin y = 8'b00; case (AluOpMuxSel) 2'b00: begin y = x0 + x1; end 2'b01: begin y = x0 - x1; end 2'b10: begin y = x0 & x1; end 2'b11: begin y = x0 | x1; end endcase end endmodule ✅ ControlUnit `timescale 1ns / 1ps module ControlUnit ( input logic clk, input logic reset, output logic RFSrcMuxSel, output logic [2:0] RAddr1, output logic [2:0] RAddr2, output logic [2:0] WAddr, output logic [1:0] AluOpMuxSel, output logic we, input logic Lt, output logic OutPortEn ); typedef enum { S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13 } state_e; state_e state, next_state; always_ff @(posedge clk or posedge reset) begin if(reset) begin state <= S0; end else begin state <= next_state; end end always_comb begin next_state = state; RFSrcMuxSel = 0; RAddr1 = 0; RAddr2 = 0; WAddr = 0; AluOpMuxSel = 0; we = 0; OutPortEn = 0; case (state) S0:begin // R1 = 1 RFSrcMuxSel = 1; RAddr1 = 0; RAddr2 = 0; WAddr = 1; AluOpMuxSel = 0; we = 1; OutPortEn = 0; next_state = S1; end S1:begin // R2 = 0 RFSrcMuxSel = 0; RAddr1 = 0; RAddr2 = 0; WAddr = 3'h2; AluOpMuxSel = 0; we = 1; OutPortEn = 0; next_state = S2; end S2:begin // R3 = 0 RFSrcMuxSel = 0; RAddr1 = 0; RAddr2 = 0; WAddr = 3'h3; AluOpMuxSel = 0; we = 1; OutPortEn = 0; next_state = S3; end S3:begin // R4 = 0 RFSrcMuxSel = 0; RAddr1 = 0; RAddr2 = 0; WAddr = 3'h4; AluOpMuxSel = 0; we = 1; OutPortEn = 0; next_state = S4; end S4:begin // R2 = R1 + R1 RFSrcMuxSel = 0; RAddr1 = 1; RAddr2 = 1; WAddr = 3'h2; AluOpMuxSel = 0; we = 1; OutPortEn = 0; next_state = S5; end S5:begin // R3 = R2 + R1 RFSrcMuxSel = 0; RAddr1 = 3'h2; RAddr2 = 1; WAddr = 3'h3; AluOpMuxSel = 0; we = 1; OutPortEn = 0; next_state = S6; end S6:begin // R4 = R3 - R1 RFSrcMuxSel = 0; RAddr1 = 3'h3; RAddr2 = 1; WAddr = 3'h4; AluOpMuxSel = 1; we = 1; OutPortEn = 0; next_state = S7; end S7:begin // R1 = R1 | R2 RFSrcMuxSel = 0; RAddr1 = 3'h1; RAddr2 = 3'h2; WAddr = 3'h1; AluOpMuxSel = 2'h3; we = 1; OutPortEn = 0; next_state = S8; end S8:begin // R4 < R2 RFSrcMuxSel = 0; RAddr1 = 3'h4; RAddr2 = 3'h2; WAddr = 0; AluOpMuxSel = 0; we = 0; OutPortEn = 0; if(Lt) next_state = S6; else next_state = S9; end S9:begin // R4 = R4 & R3 RFSrcMuxSel = 0; RAddr1 = 3'h4; RAddr2 = 3'h3; WAddr = 3'h4; AluOpMuxSel = 2'h2; we = 1; OutPortEn = 0; next_state = S10; end S10:begin // R4 = R2 + R3 RFSrcMuxSel = 0; RAddr1 = 3'h2; RAddr2 = 3'h3; WAddr = 3'h4; AluOpMuxSel = 2'h0; we = 1; OutPortEn = 0; next_state = S11; end S11:begin // R4 > R2 RFSrcMuxSel = 0; RAddr1 = 3'h4; RAddr2 = 3'h2; WAddr = 0; AluOpMuxSel = 0; we = 0; OutPortEn = 0; if(Lt) next_state = S12; else next_state = S4; end S12:begin // OutPut RFSrcMuxSel = 0; RAddr1 = 3'h4; RAddr2 = 0; WAddr = 0; AluOpMuxSel = 0; we = 0; OutPortEn = 1; next_state = S13; end S13:begin // halt RFSrcMuxSel = 0; RAddr1 = 0; RAddr2 = 0; WAddr = 0; AluOpMuxSel = 0; we = 0; OutPortEn = 0; next_state = S13; end endcase end endmodule
Study · 2025-08-12
DedicatedProcessor Adder
DedicatedProcessor Adder ✅ top.sv `timescale 1ns / 1ps module top( input logic clk, input logic reset, output logic [3:0] fndCom, output logic [7:0] fndFont ); logic [ 7:0] OutPort; logic clk_10hz; clk_divider U_CLK_DIV ( .clk (clk), .reset (reset), .clk_10hz (clk_10hz) ); DedicatedProcessor_Adder U_DedicatedProcessor_Adder ( .clk (clk_10hz), .reset (reset), .OutPort (OutPort) ); fndController U_fndController ( .clk (clk), .reset (reset), .number (OutPort), .fndCom (fndCom), .fndFont (fndFont) ); endmodule module clk_divider ( input logic clk, input logic reset, output logic clk_10hz ); logic [$clog2(10_000_000)-1:0] div_counter; always_ff @(posedge clk or posedge reset) begin if(reset) begin div_counter <= 0; clk_10hz <= 0; end else begin if(div_counter == 10_000_000 - 1)begin div_counter <= 0; clk_10hz <= 1; end else begin div_counter <= div_counter + 1; clk_10hz <= 0; end end end endmodule ✅ DedicatedProcessor_Adder.sv `timescale 1ns / 1ps module DedicatedProcessor_Adder( input logic clk, input logic reset, output logic [ 7:0] OutPort ); logic SumSrcMuxSel; logic ISrcMuxSel; logic AdderSrcMuxSel; logic SumEn; logic IEn; logic ILe10; logic OutPortEn; DataPath U_DataPath ( .clk (clk), .reset (reset), .SumSrcMuxSel (SumSrcMuxSel), .ISrcMuxSel (ISrcMuxSel), .AdderSrcMuxSel (AdderSrcMuxSel), .SumEn (SumEn), .IEn (IEn), .ILe10 (ILe10), .OutPortEn (OutPortEn), .OutPort (OutPort) ); ControlUnit U_ControlUnit ( .clk (clk), .reset (reset), .ILe10 (ILe10), .SumSrcMuxSel (SumSrcMuxSel), .ISrcMuxSel (ISrcMuxSel), .AdderSrcMuxSel (AdderSrcMuxSel), .SumEn (SumEn), .IEn (IEn), .OutPortEn (OutPortEn) ); endmodule ✅ DataPath.sv `timescale 1ns / 1ps module DataPath( input logic clk, input logic reset, input logic SumSrcMuxSel, input logic ISrcMuxSel, input logic AdderSrcMuxSel, input logic SumEn, input logic IEn, output logic ILe10, input logic OutPortEn, output logic [7:0] OutPort ); logic [7:0] SumSrcMuxOut, ISrcMuxOut; logic [7:0] SumRegOut, IRegOut; logic [7:0] AdderResult, AdderSrcMuxOut; mux_2X1 U_SumSrcMux ( .sel (SumSrcMuxSel), .x0 (0), .x1 (AdderResult), .y (SumSrcMuxOut) ); mux_2X1 U_ISrcMux ( .sel (ISrcMuxSel), .x0 (0), .x1 (AdderResult), .y (ISrcMuxOut) ); register U_SUM_REG ( .clk (clk), .reset (reset), .en (SumEn), .d (SumSrcMuxOut), .q (SumRegOut) ); register U_I_Reg ( .clk (clk), .reset (reset), .en (IEn), .d (ISrcMuxOut), .q (IRegOut) ); comparator U_ILe10 ( .a (IRegOut), .b (8'd10), .lt (ILe10) ); mux_2X1 U_AdderSrcMux ( .sel (AdderSrcMuxSel), .x0 (SumRegOut), .x1 (1), .y (AdderSrcMuxOut) ); adder U_Adder ( .a (AdderSrcMuxOut), .b (IRegOut), .sum (AdderResult) ); register U_OutPort ( .clk (clk), .reset (reset), .en (OutPortEn), .d (SumRegOut), .q (OutPort) ); endmodule ✅ ControlUnit.sv `timescale 1ns / 1ps module ControlUnit( input logic clk, input logic reset, input logic ILe10, output logic SumSrcMuxSel, output logic ISrcMuxSel, output logic AdderSrcMuxSel, output logic SumEn, output logic IEn, output logic OutPortEn ); typedef enum { S0, S1, S2, S3, S4, S5 } state_e; state_e state, next_state; always_ff @(posedge clk or posedge reset) begin if(reset) begin state <= S0; end else begin state <= next_state; end end always_comb begin next_state = state; SumSrcMuxSel = 0; ISrcMuxSel = 0; SumEn = 0; IEn = 0; AdderSrcMuxSel = 0; OutPortEn = 0; case (state) S0:begin SumSrcMuxSel = 0; ISrcMuxSel = 0; SumEn = 1; IEn = 1; AdderSrcMuxSel = 0; OutPortEn = 0; next_state = S1; end S1:begin SumSrcMuxSel = 0; ISrcMuxSel = 0; SumEn = 0; IEn = 0; AdderSrcMuxSel = 0; OutPortEn = 0; if(ILe10) next_state = S2; else next_state = S5; end S2:begin SumSrcMuxSel = 1; ISrcMuxSel = 1; SumEn = 1; IEn = 0; AdderSrcMuxSel = 0; OutPortEn = 0; next_state = S3; end S3:begin SumSrcMuxSel = 1; ISrcMuxSel = 1; SumEn = 0; IEn = 1; AdderSrcMuxSel = 1; OutPortEn = 0; next_state = S4; end S4:begin SumSrcMuxSel = 1; ISrcMuxSel = 1; SumEn = 0; IEn = 0; AdderSrcMuxSel = 0; OutPortEn = 1; next_state = S1; end S5:begin SumSrcMuxSel = 1; ISrcMuxSel = 1; SumEn = 0; IEn = 0; AdderSrcMuxSel = 0; OutPortEn = 0; next_state = S5; end endcase end endmodule
Study · 2025-08-11
DedicatedProcessor Counter
DedicatedProcessor Counter ✅ DedicatedProcessor Counter `timescale 1ns / 1ps module DedicatedProcessor_Counter( input logic clk, input logic reset, output logic [7:0] OutBuffer ); logic ASrcMuxsel, AEn, OutBufEn, ALt10; logic [$clog2(100_000_000 / 10)-1:0] div_counter; logic clk_10hz; always_ff @(posedge clk or posedge reset) begin if(reset) begin div_counter <= 0; end else begin if(div_counter == 10_000_000 - 1) begin div_counter <= 0; clk_10hz <= 1'b1; end else begin div_counter <= div_counter + 1; clk_10hz <= 0; end end end DataPath U_DataPath ( .clk (clk_10hz), .* ); ControlUnit U_ControlUnit ( .clk (clk_10hz), .* ); endmodule module DataPath( input logic clk, input logic reset, input logic ASrcMuxsel, input logic AEn, output logic ALt10, input logic OutBufEn, output logic [7:0] OutBuffer ); logic [7:0] AdderResult, ASrcMuxOut, ARegOut; mux_2X1 U_ASrcMux ( .sel (ASrcMuxsel), .x0 (8'h0), .x1 (AdderResult), .y (ASrcMuxOut) ); register U_Register ( .clk (clk), .reset (reset), .en (AEn), .d (ASrcMuxOut), .q (ARegOut) ); register U_OutReg ( .clk (clk), .reset (reset), .en (OutBufEn), .d (ARegOut), .q (OutBuffer) ); comparator U_Comparator( .a (ARegOut), .b (8'd10), .lt (ALt10) ); adder U_Adder ( .a (ARegOut), .b (8'd1), .sum (AdderResult) ); /* OutBuf U_OutBuf ( .en (OutBufEn), .x (ARegOut), .y (OutBuffer) ); */ endmodule module register ( input logic clk, input logic reset, input logic en, input logic [7:0] d, output logic [7:0] q ); always_ff @(posedge clk or posedge reset) begin if(reset) begin q <= 0; end else begin if(en) begin q <= d; end end end endmodule module mux_2X1 ( input logic sel, input logic [7:0] x0, input logic [7:0] x1, output logic [7:0] y ); always_comb begin y = 8'b0; case (sel) 1'b0: y = x0; 1'b1: y = x1; endcase end endmodule module adder ( input logic [7:0] a, input logic [7:0] b, output logic [7:0] sum ); assign sum = a + b; endmodule module comparator ( input logic [7:0] a, input logic [7:0] b, output logic lt ); assign lt = a < b; endmodule module OutBuf ( input logic en, input logic [7:0] x, output logic [7:0] y ); assign y = en ? x : 8'bx; endmodule module ControlUnit( input logic clk, input logic reset, input logic ALt10, output logic ASrcMuxsel, output logic AEn, output logic OutBufEn ); typedef enum { S0, S1, S2, S3, S4 } state_e; state_e state, next_state; always_ff @(posedge clk or posedge reset) begin if(reset) begin state <= S0; end else begin state <= next_state; end end always_comb begin next_state = state; ASrcMuxsel = 0; AEn = 0; OutBufEn = 0; case (state) S0:begin ASrcMuxsel = 0; AEn = 1; OutBufEn = 0; next_state = S1; end S1:begin ASrcMuxsel = 1; AEn = 0; OutBufEn = 0; if(ALt10) next_state = S2; else next_state = S4; end S2:begin ASrcMuxsel = 1; AEn = 0; OutBufEn = 1; next_state = S3; end S3:begin ASrcMuxsel = 1; AEn = 1; OutBufEn = 0; next_state = S1; end S4:begin ASrcMuxsel = 1; AEn = 0; OutBufEn = 0; next_state = S4; end endcase end endmodule
Study · 2025-08-11

Touch background to close