CMOS Inverter Simulation with Synopsys Custom Compiler

This guide walks through creating, simulating, and analyzing a CMOS inverter schematic using Synopsys Custom Compiler and PrimeWave.

1. Library and Cell Setup

Create a new library:

1. New → Library
2. Set attributes:
   • Name: Library name
   • Technology: Select tech library

Create a new CellView:

1. File → New → CellView
2. Configure:
   • Cell Name: Inverter
   • View Name: schematic

Design Settings:

Options → Design → Configure:

• Snap Spacing (X,Y): Grid spacing
• Solder Dot Size: Connection point size
• Fat Wire Width: Thick wire width
• Default Net Prefix: Signal prefix

2. Schematic Design

Add Components:

Use the Add tool (I=Instance, W=Wire, L=Label, P=Pin):

CMOS Inverter Schematic:

1. Place PMOS and NMOS transistors
2. Connect to VDD (top) and VSS (bottom)
3. Add input (VIN) and output (VOUT) pins

Component Properties:

Select components → Press q → Configure:

• Transistor dimensions (W/L)
• Net connections

3. Symbol Creation

Generate Symbol:

Pin Arrangement:

Final Inverter Symbol:

4. Test Schematic Setup

Create Testbench:

Add Components:

1. Inverter symbol (Instance)
2. Ground (GND)
3. Voltage source (VDC)

Configure Voltage Sources:

5. Simulation with PrimeWave

Launch PrimeWave:

Set Model Files:

Configure Simulation:

1. Model Section: Select (e.g., FF)
2. Variables: Copy from Design → Set VIN=0 (설정하지 않으면 simulation이 안나올 수 있다)
3. Simulation Engine: PrimeSim HSPICE

Run Analysis:

1. Setup → Analyses
2. Analysis Type: dc
3. DC Analysis → Design Variable
4. Variable Name, Sweep Type: VIN
5. Start, Stop, Step Size: e.g., 0, 1.8, 0.01

Run Simulation:

Results:

NOT WaveView

6. Troubleshooting

Schematic Lock Issue:

Delete lock file: *sch.oa.cdslck

Advanced Configuration:

• Variable overrides
• Simulator options

Key Notes

1. VIN Initialization: Must be set to 0V for DC sweep
2. Model Selection: Use correct technology corner (e.g., FF)
3. Port Connections: Verify VDD/VSS connections in test schematic

This structured guide ensures reproducible CMOS inverter simulation with clear visualization at each step.